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Title: Processor register error correction management

Patent ·
OSTI ID:1337630
; ;

Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B599858
Assignee:
International Business Machines Corporation (Armonk, NY
Patent Number(s):
9,529,653
Application Number:
14/510,350
OSTI ID:
1337630
Resource Relation:
Patent File Date: 2014 Oct 09
Country of Publication:
United States
Language:
English

References (11)

Soft error handling in microprocessors patent March 2009
Variable strength ECC patent June 2010
Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation conference October 2014
Exploring event correlation for failure prediction in coalitions of clusters conference January 2007
SECRET: Selective error correction for refresh energy reduction in DRAMs
  • Lin, Chung-Hsiang; Shen, De-Yu; Chen, Yi-Jung
  • 2012 IEEE 30th International Conference on Computer Design (ICCD 2012), 2012 IEEE 30th International Conference on Computer Design (ICCD) https://doi.org/10.1109/ICCD.2012.6378619
conference September 2012
Flikker: saving DRAM refresh-power through critical data partitioning journal March 2011
Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node journal June 2011
Assessment of the Impact of Cosmic-Ray-Induced Neutrons on Hardware in the Roadrunner Supercomputer journal June 2012
Technologies to further reduce soft error susceptibility in SOI conference December 2009
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs conference January 2005
32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches journal December 2011

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Related Subjects

97 MATHEMATICS AND COMPUTING