Promoting prefetched data from a cache memory to registers in a processor
Patent
·
OSTI ID:1986742
An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC52-07NA27344
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Number(s):
- 11,481,331
- Application Number:
- 17/135,832
- OSTI ID:
- 1986742
- Country of Publication:
- United States
- Language:
- English
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