Effectiveness of caches and data prefetch buffers in large-scale shared-memory multiprocessors
Large shared-memory multiprocessors usually have difficulty in matching the memory speed with the processor speed due to the large interconnection network between processors and shared memory. This thesis explores the effectiveness of caches and data prefetching by the processor in eliminating the memory-access bottleneck. Using trace-driven simulations of numerical subroutines that were transformed into parallel form, the following multiprocessor characteristics were modeled in performance evaluation: (1) the cost of a cache coherence enforcement scheme, (2) the effect of a high degree of over-lap between cache miss services, (3) the cost of a pin limited data path between shared memory and caches, (4) the effect of a high degree of data prefetching, (5) the program behavior of a scientific workload as represented by over 20 numerical subroutines, and (6) the parallel execution of programs. The optimal cache block size was examined in detail and it was found that a small cache block size is favored in the multiprocessors of interest.
- Research Organization:
- Illinois Univ., Urbana (USA)
- OSTI ID:
- 6445579
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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