Parallel digital processor
This patent describes an improvement in a general purpose parallel digital processor including a plurality of processing modules coupled to a common main memory. The improvement comprises parallel processing modules (PPM's) including: a program register for storing instruction code; at least two data registers for storing data to be processed; a separate parallel port for each of the registers to permit simultaneous transfer of data and code to the respective registers from the common main memory; an arithmetic logic unit (ALU) coupled to receive data from the data registers; an instruction decoder responsive to the instruction code stored in the program register, and operative to control the ALU to process data from the data registers according to instructions from the program register; a transfer control circuit operable in at least an input mode and an execute mode. The transfer control circuit being operative during the input mode, to transfer data to the registers via the ports from the common main memory, and during the execute mode, to transfer data to the ALU via one or more of the ports directly to the ALU, or from one or more of the registers to the ALU. The parallel digital processor further including a transfer bus network for selectively interconnecting: the PPM's during the execute mode, and the PPM's and the common memory during the input mode.
- Assignee:
- NOV; NOV-90-010175; EDB-90-083666
- Patent Number(s):
- US 4901224; A
- Application Number:
- PPN: US 6-704919A
- OSTI ID:
- 6893710
- Resource Relation:
- Patent File Date: 25 Feb 1985
- Country of Publication:
- United States
- Language:
- English
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EXECUTIVE CODES
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990200* - Mathematics & Computers