Cellular array processor with individual cell-level data-dependent cell control and multiport input memory
Patent
·
OSTI ID:6895782
In a processor array of the type including a plurality of individual processing cells, the combination therewith of a processing cell structure for inclusion in the array. The processing cell comprising: memory means having multiple input ports each for receiving separate input data from the controller and a plurality of output ports, an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of the memory means, with the arithmetic logic unit having an output port, first register means coupled to the output port of the ALU for determining the status of the cell and for providing status data, second register means coupled to the first register means and the controller and operative to receive instructions from the controller and status data from the first register means to store therein a code indicative of an operating condition for the cell.
- Assignee:
- Alcatel USA Corp., New York, NY
- Patent Number(s):
- A; US 4907148
- Application Number:
- PPN: US 7-163177A
- OSTI ID:
- 6895782
- Country of Publication:
- United States
- Language:
- English
Similar Records
Cellular array processors with variable nesting depth vector control by selective enabling of left and right neighboring processor cells
Parallel digital processor
Parallel processing system apparatus
Patent
·
Tue May 16 00:00:00 EDT 1989
·
OSTI ID:5688178
Parallel digital processor
Patent
·
Mon Feb 12 23:00:00 EST 1990
·
OSTI ID:6893710
Parallel processing system apparatus
Patent
·
Tue Oct 04 00:00:00 EDT 1988
·
OSTI ID:6600983