Program structure-based blocking
Abstract
Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1399097
- Patent Number(s):
- 9772825
- Application Number:
- 14/741,995
- Assignee:
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B599858
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2015 Jun 17
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Bertolli, Carlo, Eichenberger, Alexandre E., O'Brien, John K., and Sura, Zehra N. Program structure-based blocking. United States: N. p., 2017.
Web.
Bertolli, Carlo, Eichenberger, Alexandre E., O'Brien, John K., & Sura, Zehra N. Program structure-based blocking. United States.
Bertolli, Carlo, Eichenberger, Alexandre E., O'Brien, John K., and Sura, Zehra N. Tue .
"Program structure-based blocking". United States. https://www.osti.gov/servlets/purl/1399097.
@article{osti_1399097,
title = {Program structure-based blocking},
author = {Bertolli, Carlo and Eichenberger, Alexandre E. and O'Brien, John K. and Sura, Zehra N.},
abstractNote = {Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 26 00:00:00 EDT 2017},
month = {Tue Sep 26 00:00:00 EDT 2017}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Method and product involving translation and execution of programs by automatic partitioning and data structure allocation
patent, June 1992
- Dennis, Jack B.
- US Patent Document 5,127,104
Instruction cache system for implementing programs having non-sequential instructions and method of implementing same
patent, December 1997
- Chi, Chi-Hung
- US Patent Document 5,701,435
Method, apparatus and computer programmed product for binary re-optimization using a high level language compiler
patent, September 2001
- Goebel, Kurt J.
- US Patent Document 6,289,505
Method and apparatus for accelerating instruction fetching for a processor
patent, August 2003
- Flacks, Brian King; Meltzer, David; Silberman, Joel Abraham
- US Patent Document 6,604,191
Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted
patent, September 2004
- Morris, Dale C.; Callister, James; Undy, Stephen R.
- US Patent Document 6,799,263
Program-directed cache prefetching for media processors
patent, June 2007
- Berg, Stefan; Kim, Donglok; Kim, Yongmin
- US Patent Document 7,234,040
Method and apparatus for multicast multiple prefetch
patent, October 2007
- Jair, Hsinlun; Lo, Kaiwen
- US Patent Document 7,286,548
Instruction to load data up to a dynamically determined memory boundary
patent, October 2016
- Bradbury, Jonathan D.; Gschwind, Michael K.; Jacobi, Christian
- US Patent Document 9,471,312
Method and system of memory management using stack walking
patent-application, March 2002
- Charnell, William; Plummer, Wayne; Darnell, Stephen
- US Patent Application 09/859161; 20020029357
Method and apparatus for inserting prefetch instructions in an optimizing compiler
patent-application, May 2003
- Tirumalai, Partha; Kalogeropulos, Spiros; Rajagopalan, Mahadevan
- US Patent Application 10/052999; 20030088864
Program-directed cache prefetching for media processors
patent-application, August 2003
- Berg, Stefan; Kim, Donglok; Kim, Yongmin
- US Patent Application 10/056247; 20030154349
Signal processor, prefetch instruction method and prefetch instruction program
patent-application, September 2004
- Azuma, Tetsuhiko
- US Patent Application 10/453723; 20040181655
Zero-overhead loop operation in microprocessor having instruction buffer
patent-application, September 2004
- Ahmad, Sagheer; Knoth, Matthias; Arnold, Roger
- US Patent Application 10/396063; 20040193858
Multiple instruction set architecture code format
patent-application, December 2004
- Wang, Hong; Shen, John
- US Patent Application 10/608315; 20040268326
Prefetching Irregular Data References for Software Controlled Caches
patent-application, October 2009
- Chen, Tong; Gonzalez tallada, Marc; Sura, Zehra
- US Patent Application 12/062579; 20090254895
Sequential processor comprising an alu array
patent-application, August 2012
- Vorbach, Martin; May, Frank; Weinhardt, Markus
- US Patent Application 13/123527; 20120216012
Collision-based alternate hashing
patent-application, December 2013
- Alexander, Khary; Averbouch, Ilia; Birnbaum, Ariel
- US Patent Application 13/524139; 20130339665
Next Instruction Access Intent Instruction
patent-application, December 2013
- Jacobi, Christian; Chum, Chung-Lung; Slegel, Timothy
- US Patent Application 13/524105; 20130339672
Multi-core processors
patent-application, January 2014
- Vajda, Andras; Stenstrom, Per
- US Patent Application 14/110140; 20140033217
Extract Target Cache Attribute Facility and Instruction Therefore
patent-application, January 2015
- Greiner, Dan; Slegel, Timothy
- US Patent Application 13/941767; 20150019814
Design and evaluation of a compiler algorithm for prefetching
journal, September 1992
- Mowry, Todd C.; Lam, Monica S.; Gupta, Anoop
- ACM SIGPLAN Notices, Vol. 27, Issue 9, p. 62-73
An architecture for software-controlled data prefetching
journal, May 1991
- Klaiber, Alexander C.; Levy, Henry M.
- ACM SIGARCH Computer Architecture News, Vol. 19, Issue 3, p. 43-53
Data-Driven Multithreading Using Conventional Microprocessors
journal, October 2006
- Kyriacou, C.; Evripidou, P.; Trancoso, P.
- IEEE Transactions on Parallel and Distributed Systems, Vol. 17, Issue 10, p. 1176-1188
A Predictable Execution Model for COTS-Based Embedded Systems
conference, April 2011
- Pellizzoni, Rodolfo; Betti, Emiliano; Bak, Stanley
- 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
Integrating Caching and Prefetching Mechanisms in a Distributed Transactional Memory
journal, August 2011
- Dash, Alokika; Demsky, Brian
- IEEE Transactions on Parallel and Distributed Systems, Vol. 22, Issue 8, p. 1284-1298