Global to push GA events into
skip to main content

Title: Program structure-based blocking

Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.
Inventors:
; ; ;
Issue Date:
OSTI Identifier:
1399244
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION OSTI
Patent Number(s):
9,772,824
Application Number:
14/668,108
Contract Number:
B599858
Resource Relation:
Patent File Date: 2015 Mar 25
Research Org:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Other works cited in this record:

Byte-compare operation for high-performance processor
patent, October 1996

Instruction cache system for implementing programs having non-sequential instructions and method of implementing same
patent, December 1997

Touch history table
patent, April 2000

Branch performance in high speed processor
patent, December 2000

Multiple execution of instruction loops within a processor without accessing program memory
patent, October 2005

Method and apparatus for multicast multiple prefetch
patent, October 2007

Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations
patent, February 2010

Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations
patent, April 2013

Adaptive instruction prefetching and fetching memory system apparatus and method for microprocessor system
patent, July 2015

Method and system of memory management using stack walking
patent-application, March 2002

Method and apparatus for inserting prefetch instructions in an optimizing compiler
patent-application, May 2003

Program-directed cache prefetching for media processors
patent-application, August 2003

Signal processor, prefetch instruction method and prefetch instruction program
patent-application, September 2004

Predictively processing tasks for building software
patent-application, December 2004

Program conversion device and program conversion method
patent-application, November 2006

Prefetching Irregular Data References for Software Controlled Caches
patent-application, October 2009

Fast and Low-RAM-Footprint Indexing for Data Deduplication
patent-application, November 2011

Collision-based alternate hashing
patent-application, December 2013

Multi-core processors
patent-application, January 2014

Optimization of instruction groups across group boundaries
patent-application, January 2015

Generating and caching software code
patent-application, November 2015

Automated adaptive compiler optimization
patent-application, March 2016

Design and evaluation of a compiler algorithm for prefetching
conference, September 1992
  • Mowry, Todd C.; Lam, Monica S.; Gupta, Anoop
  • ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, Vol. 27, Issue 9, p. 62-73
  • DOI: 10.1145/143365.143488

An architecture for software-controlled data prefetching
conference, May 1991
  • Klaiber, Alexander C.; Levy, Henry M.
  • ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture, Vol. 19, Issue 3, p. 43-53
  • DOI: 10.1145/115952.115958

Impulse: building a smarter memory controller
conference, August 2002
  • Carter, J.; Hsieh, W.; Stoller, L.
  • Proceedings Fifth International Symposium on High-Performance Computer Architecture
  • DOI: 10.1109/HPCA.1999.744334

Prefetching and memory system behavior of the SPEC95 benchmark suite
journal, May 1997
  • Charney, M. J.; Puzak, T. R.
  • IBM Journal of Research and Development, Vol. 41, Issue 3, p. 265-286
  • DOI: 10.1147/rd.413.0265

Making pointer-based data structures cache conscious
journal, January 2000
  • Larus, J. R.; Hill, M. D.; Chilimbi, T. M.
  • Computer, Vol. 33, Issue 12, p. 67-74
  • DOI: 10.1109/2.889095

Comparing memory systems for chip multiprocessors
conference, May 2007
  • Leverich, Jacob; Arakida, Hideho; Solomatnikov, Alex
  • ISCA '07 Proceedings of the 34th annual international symposium on Computer architecture, Vol. 35, Issue 2, p. 358-368
  • DOI: 10.1145/1250662.1250707

Similar records in DOepatents and OSTI.GOV collections: