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Title: Low latency memory access and synchronization

Abstract

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

Inventors:
 [1];  [2];  [3];  [4];  [5];  [6];  [7];  [8];  [4];  [4];  [9]
  1. Ridgefield, CT
  2. Croton On Hudson, NY
  3. Yorktown Heights, NY
  4. Mount Kisco, NY
  5. Irvington, NY
  6. Cortlandt Manor, NY
  7. Ossining, NY
  8. Brewster, NY
  9. Bedford Hills, NY
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
949197
Patent Number(s):
7174434
Application Number:
10/468,994
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
H - ELECTRICITY H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR H05K - PRINTED CIRCUITS
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B517552
Resource Type:
Patent
Country of Publication:
United States
Language:
English

Citation Formats

Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Ohmacht, Martin, Steinmacher-Burow, Burkhard D, Takken, Todd E, and Vranas, Pavlos M. Low latency memory access and synchronization. United States: N. p., 2007. Web.
Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Ohmacht, Martin, Steinmacher-Burow, Burkhard D, Takken, Todd E, & Vranas, Pavlos M. Low latency memory access and synchronization. United States.
Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Ohmacht, Martin, Steinmacher-Burow, Burkhard D, Takken, Todd E, and Vranas, Pavlos M. Tue . "Low latency memory access and synchronization". United States. https://www.osti.gov/servlets/purl/949197.
@article{osti_949197,
title = {Low latency memory access and synchronization},
author = {Blumrich, Matthias A and Chen, Dong and Coteus, Paul W and Gara, Alan G and Giampapa, Mark E and Heidelberger, Philip and Hoenicke, Dirk and Ohmacht, Martin and Steinmacher-Burow, Burkhard D and Takken, Todd E and Vranas, Pavlos M},
abstractNote = {A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2007},
month = {2}
}

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