Method and apparatus for reducing memory access latency

Roberts, David A.

Title: Method and apparatus for reducing memory access latency

Abstract

Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.

Inventors:: Roberts, David A.

Issue Date:: 2019-12-24

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1600430

Patent Number(s):: 10515671

Application Number:: 15/272,894

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

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G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C7/222 - {Clock generating, synchronizing or distributing circuits within memory device}
G11C2029/0409 - {Online test}
G11C7/00 - Arrangements for writing information into, or reading information out from, a digital store

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DOE Contract Number:: AC52-07NA27344; B608045

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/22/2016

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Roberts, David A. Method and apparatus for reducing memory access latency.  United States: N. p., 2019. 
        Web.

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                    Roberts, David A. Method and apparatus for reducing memory access latency.  United States.

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                    Roberts, David A. Tue .  
        "Method and apparatus for reducing memory access latency".  United States.  https://www.osti.gov/servlets/purl/1600430.

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@article{osti_1600430,

  title        = {Method and apparatus for reducing memory access latency},

  author       = {Roberts, David A.},

  abstractNote = {Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {12}

}

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Title: Method and apparatus for reducing memory access latency

Abstract

Citation Formats

Bridge for coupling digital signal processor to on-chip bus as slave patent, September 2004

Apparatus and method for copying and restoring disk files patent, July 1996

Computer memory system with a low power down mode patent, June 2001

Backup technique for data stored on multiple storage devices patent, August 2006

Method and apparatus for collapsing writebacks to a memory for resource efficiency patent, August 2002

Concurrent image backup for disk storage system patent, January 1996

System and method for dynamic clock generation patent, December 2007

Remote copy system with data integrity patent, March 2004

Data storage with host-initiated synchronization and fail-over of remote mirror patent, February 2004

Method and system of copying memory from a source processor to a target processor by duplicating memory writes patent, September 2009

Techniques for improving memory access in a virtual memory system patent, August 2002

Method and apparatus for partial memory power shutoff patent, August 2006

System and method for dynamic clock generation patent, May 2003

Cache memory for efficient data logging patent, April 1999

Method and apparatus for providing a disc drive snapshot backup while allowing normal drive read, write, and buffering operations patent, January 2001

Snapshot copy facility for a data storage system permitting continued host read/write access patent, August 2002

Bridge for coupling digital signal processor to on-chip bus as slave
patent, September 2004

Apparatus and method for copying and restoring disk files
patent, July 1996

Computer memory system with a low power down mode
patent, June 2001

Backup technique for data stored on multiple storage devices
patent, August 2006

Method and apparatus for collapsing writebacks to a memory for resource efficiency
patent, August 2002

Concurrent image backup for disk storage system
patent, January 1996

System and method for dynamic clock generation
patent, December 2007

Remote copy system with data integrity
patent, March 2004

Data storage with host-initiated synchronization and fail-over of remote mirror
patent, February 2004

Method and system of copying memory from a source processor to a target processor by duplicating memory writes
patent, September 2009

Techniques for improving memory access in a virtual memory system
patent, August 2002

Method and apparatus for partial memory power shutoff
patent, August 2006

System and method for dynamic clock generation
patent, May 2003

Cache memory for efficient data logging
patent, April 1999

Method and apparatus for providing a disc drive snapshot backup while allowing normal drive read, write, and buffering operations
patent, January 2001

Snapshot copy facility for a data storage system permitting continued host read/write access
patent, August 2002