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Title: Method and apparatus for reducing memory access latency

Abstract

Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.

Inventors:
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1600430
Patent Number(s):
10515671
Application Number:
15/272,894
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
DOE Contract Number:  
AC52-07NA27344; B608045
Resource Type:
Patent
Resource Relation:
Patent File Date: 09/22/2016
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Roberts, David A. Method and apparatus for reducing memory access latency. United States: N. p., 2019. Web.
Roberts, David A. Method and apparatus for reducing memory access latency. United States.
Roberts, David A. Tue . "Method and apparatus for reducing memory access latency". United States. https://www.osti.gov/servlets/purl/1600430.
@article{osti_1600430,
title = {Method and apparatus for reducing memory access latency},
author = {Roberts, David A.},
abstractNote = {Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {12}
}

Patent:

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