Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Ohmacht, Martin

Title: Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Abstract

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Inventors:: Ohmacht, Martin

Issue Date:: 2014-09-09

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1156947

Patent Number(s):: 8832403

Application Number:: 12/796,411

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C7/22 - Read-write [R-W] timing or clocking circuits

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/3004 - {to perform operations on memory}
G06F2003/0697 - {device management, e.g. handlers, drivers, I/O schedulers}
G06F13/1689 - {Synchronisation and timing concerns
G06F9/522 - {Barrier synchronisation}
G06F9/30047 - {Prefetch instructions
G06F3/0671 - {In-line storage system}
G06F9/3834 - {Maintaining memory consistency
G06F9/30087 - {Synchronisation or serialisation instructions}
G06F3/0655 - {Vertical data movement, i.e. input-output transfer
G06F3/0604 - {Improving or facilitating administration, e.g. storage management}

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Ohmacht, Martin. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses.  United States: N. p., 2014. 
        Web.

Copy to clipboard


                    Ohmacht, Martin. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses.  United States.

Copy to clipboard


                    Ohmacht, Martin. Tue .  
        "Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses".  United States.  https://www.osti.gov/servlets/purl/1156947.

Copy to clipboard


                    
@article{osti_1156947,

  title        = {Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses},

  author       = {Ohmacht, Martin},

  abstractNote = {In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2014},

  month        = {9}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Translation-lookaside buffer consistency
journal, June 1990

Teller, P. J.
Computer, Vol. 23, Issue 6, p. 26-36
https://doi.org/10.1109/2.55498

Storage in the power PC
journal, April 1995

Stone, J. M.; Fitzgerald, R. P.
IEEE Micro, Vol. 15, Issue 2
https://doi.org/10.1109/40.372352

A Burst Scheduling Access Reordering Mechanism
conference, February 2007

Shao, Jun; Davis, Brian T.
https://doi.org/10.1109/HPCA.2007.346206

A “card-marking” scheme for controlling intergenerational references in generation-based garbage collection on stock hardware
journal, May 1989

Wilson, P. R.; Moher, T. G.
ACM SIGPLAN Notices, Vol. 24, Issue 5
https://doi.org/10.1145/66068.66077

Similar Records in DOE Patents and OSTI.GOV collections:

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Patent Ohmacht, Martin

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.
Full Text Available
Using predictions of outcomes of cache memory access requests for controlling whether a request generator sends memory access requests to a memory in parallel with cache memory access requests

Patent Yin, Jieming; Eckert, Yasuko; Poremba, Matthew R.; ...

An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, whenmore » « less
Full Text Available
Low latency memory access and synchronization

Patent Blumrich, Matthias A [Ridgefield, CT]; Chen, Dong [Croton On Hudson, NY]; Coteus, Paul W [Yorktown Heights, NY]; ...

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » « less
Full Text Available
Low latency memory access and synchronization

Patent Blumrich, Matthias A [Ridgefield, CT]; Chen, Dong [Croton On Hudson, NY]; Coteus, Paul W [Yorktown Heights, NY]; ...

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » « less
Full Text Available
Anti-islanding protection systems for synchronous machine based distributed generators

Patent Ye, Zhihong; Du, Pengwei; Nelson, John Keith; ...

A system for providing anti-islanding protection of a synchronous machine based distributed generator includes a frequency sensor configured to generate a generator frequency signal, a bandpass filter configured for filtering the generator frequency signal, a governor controller configured for using the filtered frequency signal to generate a power feedback signal, and a governor summation element configured for summing the filtered frequency signal, the power feedback signal, and a reference power to provide an electrical torque signal. Another system includes a voltage sensor configured to generate a generator terminal voltage signal, a feedback power calculator configured for generating a reactive feedbackmore » « less
Full Text Available

Similar Records

Title: Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Abstract

Citation Formats

Translation-lookaside buffer consistency journal, June 1990

Storage in the power PC journal, April 1995

A Burst Scheduling Access Reordering Mechanism conference, February 2007

A “card-marking” scheme for controlling intergenerational references in generation-based garbage collection on stock hardware journal, May 1989

Translation-lookaside buffer consistency
journal, June 1990

Storage in the power PC
journal, April 1995

A Burst Scheduling Access Reordering Mechanism
conference, February 2007

A “card-marking” scheme for controlling intergenerational references in generation-based garbage collection on stock hardware
journal, May 1989