Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Ohmacht, Martin

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Title: Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Abstract

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Inventors:: Ohmacht, Martin

Issue Date:: 2014-09-09

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1156947

Patent Number(s):: 8832403

Application Number:: 12/796,411

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F13/1689 - {Synchronisation and timing concerns
G06F2003/0697 - {device management, e.g. handlers, drivers, I/O schedulers}
G06F3/0604 - {Improving or facilitating administration, e.g. storage management}
G06F3/0655 - {Vertical data movement, i.e. input-output transfer
G06F3/0671 - {In-line storage system}
G06F9/3004 - {to perform operations on memory}
G06F9/30047 - {Prefetch instructions
G06F9/30087 - {Synchronisation or serialisation instructions}
G06F9/3834 - {Maintaining memory consistency
G06F9/522 - {Barrier synchronisation}

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C7/22 - Read-write [R-W] timing or clocking circuits

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Ohmacht, Martin. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses.  United States: N. p., 2014. 
        Web.

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                    Ohmacht, Martin. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses.  United States.

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                    Ohmacht, Martin. Tue .  
        "Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses".  United States.  https://www.osti.gov/servlets/purl/1156947.

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@article{osti_1156947,

  title        = {Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses},

  author       = {Ohmacht, Martin},

  abstractNote = {In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2014},

  month        = {9}

}

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Similar Records

Title: Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Abstract

Citation Formats

GVT-NET--A Global Virtual Time Calculation Apparatus for Multi-Stage Networks patent, October 1993

Barrier synchronization for distributed memory massively parallel processing systems patent, July 1995

Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state patent, July 1997

Method and apparatus for storing vector data in multiple non-consecutive locations in a data processor using a mask value patent, April 1998

System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO patent, April 1999

Digital filter processing device patent, July 1999

Generation isolation system and method for garbage collection patent, August 2000

Nested parallel language preprocessor for converting parallel language programs into sequential code patent, August 2000

Replicated resource management system for managing resources in a distributed application and maintaining a relativistic view of state patent, May 2001

Method, apparatus, and article of manufacture for facilitating resource management for applications having two types of program code patent, June 2001

System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction patent, February 2002

Synchronization using bus arbitration control for system analysis patent, September 2003

Mechanism for folding storage barrier operations in a multiprocessor system patent, April 2004

Method and apparatus for multithreaded processing of data in a programmable graphics processor patent, March 2006

Specializing write-barriers for objects in a garbage collected heap patent, August 2006

Apparatus and method of moving picture encoding employing a plurality of processors patent, November 2007

Barrier synchronization method and apparatus for work-stealing threads patent, May 2011

Replicated resource management system for managing resources in a distributed application and maintaining a relativistic view of state patent-application, November 2001

Distributed shared memory system with variable granularity patent-application, January 2002

Full multiprocessor speculation mechanism in a symmetric multiprocessor (smp) System patent-application, July 2002

Multiprocessor system having distributed shared memory and instruction scheduling method used in the same system patent-application, May 2003

Method and Apparatus for Converting a Lightweight Monitor to a Heavyweight Monitor patent-application, May 2003

Method and apparatus for efficient and precise datarace detection for multithreaded object-oriented programs patent-application, December 2003

Remembered-set scrubbing to remove stale entries in an incremental garbage collector patent-application, September 2004

Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment patent-application, February 2006

Increasing data locality of recently accessed resources patent-application, March 2006

System and method for adaptive garbage collection in a virtual machine environment patent-application, October 2006

Memory consistency protection in a multiprocessor computing system patent-application, June 2008

Distributed Loop Controller Architecture for Multi-threading in Uni-threaded Processors patent-application, November 2008

Synchronisation patent-application, January 2009

System and Method for Improving Run-Time Performance of Applications with Multithreaded and Single Threaded Routines patent-application, February 2010

Translation-lookaside buffer consistency journal, June 1990

Storage in the power PC journal, April 1995

A Burst Scheduling Access Reordering Mechanism conference, February 2007

A “card-marking” scheme for controlling intergenerational references in generation-based garbage collection on stock hardware journal, May 1989

GVT-NET--A Global Virtual Time Calculation Apparatus for Multi-Stage Networks
patent, October 1993

Barrier synchronization for distributed memory massively parallel processing systems
patent, July 1995

Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state
patent, July 1997

Method and apparatus for storing vector data in multiple non-consecutive locations in a data processor using a mask value
patent, April 1998

System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO
patent, April 1999

Digital filter processing device
patent, July 1999

Generation isolation system and method for garbage collection
patent, August 2000

Nested parallel language preprocessor for converting parallel language programs into sequential code
patent, August 2000

Replicated resource management system for managing resources in a distributed application and maintaining a relativistic view of state
patent, May 2001

Method, apparatus, and article of manufacture for facilitating resource management for applications having two types of program code
patent, June 2001

System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction
patent, February 2002

Synchronization using bus arbitration control for system analysis
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Mechanism for folding storage barrier operations in a multiprocessor system
patent, April 2004

Method and apparatus for multithreaded processing of data in a programmable graphics processor
patent, March 2006

Specializing write-barriers for objects in a garbage collected heap
patent, August 2006

Apparatus and method of moving picture encoding employing a plurality of processors
patent, November 2007

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patent, May 2011

Replicated resource management system for managing resources in a distributed application and maintaining a relativistic view of state
patent-application, November 2001

Distributed shared memory system with variable granularity
patent-application, January 2002

Full multiprocessor speculation mechanism in a symmetric multiprocessor (smp) System
patent-application, July 2002

Multiprocessor system having distributed shared memory and instruction scheduling method used in the same system
patent-application, May 2003

Method and Apparatus for Converting a Lightweight Monitor to a Heavyweight Monitor
patent-application, May 2003

Method and apparatus for efficient and precise datarace detection for multithreaded object-oriented programs
patent-application, December 2003

Remembered-set scrubbing to remove stale entries in an incremental garbage collector
patent-application, September 2004

Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
patent-application, February 2006

Increasing data locality of recently accessed resources
patent-application, March 2006

System and method for adaptive garbage collection in a virtual machine environment
patent-application, October 2006

Memory consistency protection in a multiprocessor computing system
patent-application, June 2008

Distributed Loop Controller Architecture for Multi-threading in Uni-threaded Processors
patent-application, November 2008

Synchronisation
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System and Method for Improving Run-Time Performance of Applications with Multithreaded and Single Threaded Routines
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Translation-lookaside buffer consistency
journal, June 1990

Storage in the power PC
journal, April 1995

A Burst Scheduling Access Reordering Mechanism
conference, February 2007

A “card-marking” scheme for controlling intergenerational references in generation-based garbage collection on stock hardware
journal, May 1989