Optimizing software-directed instruction replication for GPU error detection
Abstract
Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.
- Inventors:
- Issue Date:
- Research Org.:
- NVIDIA Corp., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1771561
- Patent Number(s):
- 10817289
- Application Number:
- 16/150,410
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B620719
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 10/03/2018
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Hari, Siva, Sullivan, Michael, Tsai, Timothy, Keckler, Stephen W., and Mahmoud, Abdulrahman. Optimizing software-directed instruction replication for GPU error detection. United States: N. p., 2020.
Web.
Hari, Siva, Sullivan, Michael, Tsai, Timothy, Keckler, Stephen W., & Mahmoud, Abdulrahman. Optimizing software-directed instruction replication for GPU error detection. United States.
Hari, Siva, Sullivan, Michael, Tsai, Timothy, Keckler, Stephen W., and Mahmoud, Abdulrahman. Tue .
"Optimizing software-directed instruction replication for GPU error detection". United States. https://www.osti.gov/servlets/purl/1771561.
@article{osti_1771561,
title = {Optimizing software-directed instruction replication for GPU error detection},
author = {Hari, Siva and Sullivan, Michael and Tsai, Timothy and Keckler, Stephen W. and Mahmoud, Abdulrahman},
abstractNote = {Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Oct 27 00:00:00 EDT 2020},
month = {Tue Oct 27 00:00:00 EDT 2020}
}
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Works referenced in this record:
Fingerprinting of Redundant Threads Using Compiler-Inserted Transformation Code
patent-application, December 2017
- Lowell, Daniel I.
- US Patent Application 15/188304; 20170364332
Detecting and mitigating soft errors using duplicative instructions
patent-application, December 2002
- Saulsbury, Ashley N.
- US Patent Application 10/180580; 20020199175
Error detection method and system for processors that employs lockstepped concurrent threads
patent-application, May 2005
- Stafford, Kevin D.; Soltis, Jr., Donald C.; Undy, Stephen R.
- US Patent Application 10/714093; 20050108509
Reliable Execution Using Compare and Transfer Instructions on an SMT Machine
patent-application, November 2010
- Sudhakar, Ranganathan; Quach, Nhon T.
- US Patent Application 12/432146; 20100281239