Optimizing branch re-wiring in a software instruction cache
Abstract
A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1735295
- Patent Number(s):
- 10782973
- Application Number:
- 14/712,253
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- DOE Contract Number:
- B599858
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 05/14/2015
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Bertolli, Carlo, O'Brien, John Kevin Patrick, Eichenberger, Alexandre E., and Sura, Zehra Noman. Optimizing branch re-wiring in a software instruction cache. United States: N. p., 2020.
Web.
Bertolli, Carlo, O'Brien, John Kevin Patrick, Eichenberger, Alexandre E., & Sura, Zehra Noman. Optimizing branch re-wiring in a software instruction cache. United States.
Bertolli, Carlo, O'Brien, John Kevin Patrick, Eichenberger, Alexandre E., and Sura, Zehra Noman. Tue .
"Optimizing branch re-wiring in a software instruction cache". United States. https://www.osti.gov/servlets/purl/1735295.
@article{osti_1735295,
title = {Optimizing branch re-wiring in a software instruction cache},
author = {Bertolli, Carlo and O'Brien, John Kevin Patrick and Eichenberger, Alexandre E. and Sura, Zehra Noman},
abstractNote = {A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {9}
}
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Works referenced in this record:
Software-based instruction caching for embedded processors
journal, October 2006
- Miller, Jason E.; Agarwal, Anant
- ACM SIGARCH Computer Architecture News, Vol. 34, Issue 5