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Title: System and method for protecting GPU memory instructions against faults

Abstract

A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1771714
Patent Number(s):
10860418
Application Number:
16/378,287
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 04/08/2019
Country of Publication:
United States
Language:
English

Citation Formats

Kalamatianos, John, Mantor, Michael, and Gurumurthi, Sudhanva. System and method for protecting GPU memory instructions against faults. United States: N. p., 2020. Web.
Kalamatianos, John, Mantor, Michael, & Gurumurthi, Sudhanva. System and method for protecting GPU memory instructions against faults. United States.
Kalamatianos, John, Mantor, Michael, and Gurumurthi, Sudhanva. Tue . "System and method for protecting GPU memory instructions against faults". United States. https://www.osti.gov/servlets/purl/1771714.
@article{osti_1771714,
title = {System and method for protecting GPU memory instructions against faults},
author = {Kalamatianos, John and Mantor, Michael and Gurumurthi, Sudhanva},
abstractNote = {A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {12}
}

Works referenced in this record:

Real-world design and evaluation of compiler-managed GPU redundant multithreading
conference, June 2014


System and method for protecting GPU memory instructions against faults
patent, April 2019