System and methods for hardware-software cooperative pipeline error detection

Sullivan, Michael; Hari, Siva; Zimmer, Brian; Tsai, Timothy; Keckler, Stephen W.

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Title: System and methods for hardware-software cooperative pipeline error detection

Abstract

An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

Inventors:: Sullivan, Michael; Hari, Siva; Zimmer, Brian; Tsai, Timothy; Keckler, Stephen W.

Issue Date:: 2022-08-09

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1924970

Patent Number(s):: 11409597

Application Number:: 16/811,499

Assignee:: Nvidia Corp. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/0715 - {in a system implementing multitasking
G06F11/0724 - {in a multiprocessor or a multi-core unit
G06F11/0772 - {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
G06F11/102 - {Error in check bits}
G06F11/1044 - {with specific ECC/EDC distribution}
G06F11/1048 - {using arrangements adapted for a specific error detection or correction feature}
G06F11/1641 - {where the comparison is not performed by the redundant processing components}
G06F11/1654 - {where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O}
G06F9/30029 - {Logical and Boolean instructions, e.g. XOR, NOT}
G06F9/30116 - {Shadow registers, e.g. coupled registers, not forming part of the register space}

Show less

DOE Contract Number:: B620719

Resource Type:: Patent

Resource Relation:: Patent File Date: 03/06/2020

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Sullivan, Michael, Hari, Siva, Zimmer, Brian, Tsai, Timothy, and Keckler, Stephen W. System and methods for hardware-software cooperative pipeline error detection.  United States: N. p., 2022. 
        Web.

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                    Sullivan, Michael, Hari, Siva, Zimmer, Brian, Tsai, Timothy, & Keckler, Stephen W. System and methods for hardware-software cooperative pipeline error detection.  United States.

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                    Sullivan, Michael, Hari, Siva, Zimmer, Brian, Tsai, Timothy, and Keckler, Stephen W. Tue .  
        "System and methods for hardware-software cooperative pipeline error detection".  United States.  https://www.osti.gov/servlets/purl/1924970.

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@article{osti_1924970,

  title        = {System and methods for hardware-software cooperative pipeline error detection},

  author       = {Sullivan, Michael and Hari, Siva and Zimmer, Brian and Tsai, Timothy and Keckler, Stephen W.},

  abstractNote = {An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2022},

  month        = {8}

}

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Similar Records

Title: System and methods for hardware-software cooperative pipeline error detection

Abstract

Citation Formats

Error Corrections Coding Over Multiple Memory Pages patent-application, October 2013

Integrated circuit device and method for reducing SRAM leakage patent-application, February 2017

Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design journal, November 1971

Method and apparatus for providing error correction within a register file of a CPU patent, June 2006

Processor register error correction management patent, December 2016

Tolerating soft errors by selective duplication patent-application, December 2011

Method and apparatus for providing error correction within a register file of a CPU patent-application, November 2003

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses patent, May 2010

System and apparatus for error-correcting register files patent, October 2012

System and method for testing a logic-based processing device patent-application, December 2015

System and apparatus for error-correcting register files patent-application, February 2011

Semiconductor Memory Devices and Memory Systems Including the Same patent-application, April 2017

Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection conference, March 2007

Error detection by duplicated instructions in super-scalar processors journal, March 2002

Error correction for flash memory patent-application, May 2010

Error correction code memory system with a small footprint and byte write operation patent, November 2009

Error correction method with instruction level rollback patent, January 2012

Fault Free Store Data Path for Software Implementation of Redundant Multithreading Environments patent-application, July 2006

Real-world design and evaluation of compiler-managed GPU redundant multithreading conference, June 2014

SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection conference, October 2018

Error detection method and system for processors that employ alternating threads patent-application, June 2005

Understanding software approaches for GPGPU reliability conference, March 2009

Instruction and logic for support of code modification patent-application, October 2015

Error Corrections Coding Over Multiple Memory Pages
patent-application, October 2013

Integrated circuit device and method for reducing SRAM leakage
patent-application, February 2017

Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design
journal, November 1971

Method and apparatus for providing error correction within a register file of a CPU
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Processor register error correction management
patent, December 2016

Tolerating soft errors by selective duplication
patent-application, December 2011

Method and apparatus for providing error correction within a register file of a CPU
patent-application, November 2003

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses
patent, May 2010

System and apparatus for error-correcting register files
patent, October 2012

System and method for testing a logic-based processing device
patent-application, December 2015

System and apparatus for error-correcting register files
patent-application, February 2011

Semiconductor Memory Devices and Memory Systems Including the Same
patent-application, April 2017

Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection
conference, March 2007

Error detection by duplicated instructions in super-scalar processors
journal, March 2002

Error correction for flash memory
patent-application, May 2010

Error correction code memory system with a small footprint and byte write operation
patent, November 2009

Error correction method with instruction level rollback
patent, January 2012

Fault Free Store Data Path for Software Implementation of Redundant Multithreading Environments
patent-application, July 2006

Real-world design and evaluation of compiler-managed GPU redundant multithreading
conference, June 2014

SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection
conference, October 2018

Error detection method and system for processors that employ alternating threads
patent-application, June 2005

Understanding software approaches for GPGPU reliability
conference, March 2009

Instruction and logic for support of code modification
patent-application, October 2015