Method and apparatus for power delivery to a die stack via a heat spreader

Yudanov, Dmitri

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A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
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A44 - haberdashery
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A47 - furniture
A61 - medical or veterinary science
A62 - life-saving
A63 - sports
A99 - subject matter not otherwise provided for in this section
B - performing operations
B01 - physical or chemical processes or apparatus in general
B02 - crushing, pulverising, or disintegrating
B03 - separation of solid materials using liquids or using pneumatic tables or jigs
B04 - centrifugal apparatus or machines for carrying-out physical or chemical processes
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B22 - casting
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Title: Method and apparatus for power delivery to a die stack via a heat spreader

Abstract

Various chip stack power delivery circuits are disclosed. In one aspect, an apparatus is provided that includes a stack of semiconductor chips that has an uppermost semiconductor chip and a lowermost semiconductor chip. A heat spreader is positioned on the uppermost semiconductor chip. A power transfer circuit is configured to transfer electric power from the heat spreader to the uppermost semiconductor chip.

Inventors:: Yudanov, Dmitri

Issue Date:: 2020-01-07

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1632416

Patent Number(s):: 10529677

Application Number:: 15/965,425

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L2224/05624 - Aluminium [Al] as principal constituent
H01L2224/05639 - Silver [Ag] as principal constituent
H01L2224/05644 - Gold [Au] as principal constituent
H01L2224/05647 - Copper [Cu] as principal constituent
H01L2224/13 - of an individual bump connector
H01L2224/13111 - Tin [Sn] as principal constituent
H01L2224/13124 - Aluminium [Al] as principal constituent
H01L2224/13139 - Silver [Ag] as principal constituent
H01L2224/13144 - Gold [Au] as principal constituent
H01L2224/13147 - Copper [Cu] as principal constituent
H01L2224/16145 - the bodies being stacked
H01L2224/16227 - the bump connector connecting to a bond pad of the item
H01L2224/17181 - On opposite sides of the body
H01L2224/29199 - Material of the matrix
H01L2224/293 - with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
H01L2224/32245 - the item being metallic
H01L2224/37099 - Material
H01L2224/40135 - Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
H01L2224/45099 - Material
H01L2224/48145 - the bodies being stacked
H01L2224/48227 - connecting the wire to a bond pad of the item
H01L2224/4918 - being disposed on at least two different sides of the body, e.g. dual array
H01L2224/73207 - Bump and wire connectors
H01L2224/73253 - Bump and layer connectors
H01L2224/73257 - Bump and wire connectors
H01L2225/06513 - Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
H01L2225/06517 - Bump or bump-like direct electrical connections from device to substrate
H01L23/3128 - {the substrate having spherical bumps for external connection}
H01L23/3157 - {Partial encapsulation or coating
H01L23/34 - Arrangements for cooling, heating, ventilating or temperature compensation {
H01L23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks {
H01L23/5286 - {Arrangements of power or ground buses}
H01L23/645 - {Inductive arrangements
H01L24/09 - {of a plurality of bonding areas}
H01L24/16 - {of an individual bump connector}
H01L24/17 - {of a plurality of bump connectors}
H01L24/48 - {of an individual wire connector}
H01L24/49 - {of a plurality of wire connectors}
H01L24/73 - {Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71}
H01L25/0657 - {Stacked arrangements of devices}
H01L25/16 - the devices being of types provided for in two or more different main groups of H01L27/00 - H01L49/00 {and H01L51/00}, e.g. forming hybrid circuits {
H01L2924/00013 - Fully indexed content
H01L2924/00014 - the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
H01L2924/01029 - Copper [Cu]
H01L2924/01047 - Silver [Ag]
H01L2924/0105 - Tin [Sn]
H01L2924/013 - Alloys
H01L2924/014 - Solder alloys

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DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 04/27/2018

Country of Publication:: United States

Language:: English

Subject:: 42 ENGINEERING

Citation Formats


                    Yudanov, Dmitri. Method and apparatus for power delivery to a die stack via a heat spreader.  United States: N. p., 2020. 
        Web.

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                    Yudanov, Dmitri. Method and apparatus for power delivery to a die stack via a heat spreader.  United States.

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                    Yudanov, Dmitri. Tue .  
        "Method and apparatus for power delivery to a die stack via a heat spreader".  United States.  https://www.osti.gov/servlets/purl/1632416.

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@article{osti_1632416,

  title        = {Method and apparatus for power delivery to a die stack via a heat spreader},

  author       = {Yudanov, Dmitri},

  abstractNote = {Various chip stack power delivery circuits are disclosed. In one aspect, an apparatus is provided that includes a stack of semiconductor chips that has an uppermost semiconductor chip and a lowermost semiconductor chip. A heat spreader is positioned on the uppermost semiconductor chip. A power transfer circuit is configured to transfer electric power from the heat spreader to the uppermost semiconductor chip.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {1}

}

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Works referenced in this record:

Power Distribution and Thermal Solution for Direct Stacked Integrated Circuits
patent-application, August 2014

Henderson, Brian M.; Gu, Shiqun
US Patent Application 13/783124; 20140225248
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140225248

Heat Sink
patent-application, October 2014

Ng, Kah Hoe; Poh, Tzye Perng; Ng, Kay Seah
US Patent Application 13/870650
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140321062

Power Delivery to Three-Dimensional Chips
patent-application, June 2015

Mathiyalagan, Vijay A.; Pullelli, Siva Rama K.; Sethuraman, Saravanan
US Patent Application 14/132506; 20150168972
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150168972

Methods for assembling multiple semiconductor devices
patent, April 2007

Jiang, Tongbi; Fee, Setho Sing; Yean, Tay Wuu
US Patent Document 7,198,980
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7198980

Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same
patent-application, September 2017

Yu, Chen-Hua; Chang, Chih-Yuan; Wang, Chuei-Tang
US Patent Application 15/169857; 20170263518
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170263518

Die Stacking with Coupled Electrical Interconnects to Align Proximity Interconnects
patent-application, October 2013

Black, Bryan; Su, Michael; McLellan, Neil
US Patent Application 13/436094; 20130256913
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130256913

Stacked-Chip Device
patent-application, March 2010

Urakawa, Yukihiro
US Patent Application 12/546109; 20100052111
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100052111

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Similar Records

Title: Method and apparatus for power delivery to a die stack via a heat spreader

Abstract

Citation Formats

Power Distribution and Thermal Solution for Direct Stacked Integrated Circuits patent-application, August 2014

Heat Sink patent-application, October 2014

Power Delivery to Three-Dimensional Chips patent-application, June 2015

Methods for assembling multiple semiconductor devices patent, April 2007

Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same patent-application, September 2017

Die Stacking with Coupled Electrical Interconnects to Align Proximity Interconnects patent-application, October 2013

Stacked-Chip Device patent-application, March 2010

Power Distribution and Thermal Solution for Direct Stacked Integrated Circuits
patent-application, August 2014

Heat Sink
patent-application, October 2014

Power Delivery to Three-Dimensional Chips
patent-application, June 2015

Methods for assembling multiple semiconductor devices
patent, April 2007

Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same
patent-application, September 2017

Die Stacking with Coupled Electrical Interconnects to Align Proximity Interconnects
patent-application, October 2013

Stacked-Chip Device
patent-application, March 2010