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Title: Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate

Patent ·
OSTI ID:1165129

Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC04-94AL85000
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Number(s):
8,906,803
Application Number:
14/063,152
OSTI ID:
1165129
Resource Relation:
Patent File Date: 2013 Oct 25
Country of Publication:
United States
Language:
English

References (20)

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Method of anisotropically etching silicon patent March 1996
Method for fabricating silicon cells patent August 1998
Silicon solar cells made by a self-aligned, selective-emitter, plasma-etchback process patent February 1999
High-efficiency solar cell and method for fabrication patent August 1999
Laminated photovoltaic modules using back-contact solar cells patent September 1999
Method of monolithic module assembly patent October 1999
Silicon cells made by self-aligned selective-emitter plasma-etchback process patent July 2000
InGaAsN/GaAs heterojunction for multi-junction solar cells patent June 2001
Methods relating to trench-based support structures for semiconductor devices patent April 2011
Through substrate vias for back-side interconnections on very thin semiconductor wafers patent May 2011
Semiconductor die singulation method patent August 2011
Die singulation method and package formed thereby patent August 2012
Stacked die assemblies including TSV die patent November 2012
3-D circuits with integrated passive devices patent January 2013
Die singulation method patent June 2013
Lead Frame and Method of Forming Same patent-application March 2011
Integrated Circuit Packaging System with Package-on-Package Stacking and Method of Manufacture Thereof patent-application April 2011
Pass-Through 3D Interconnect for Microelectronics Dies and Associated Systems and Methods patent-application April 2012
Multi-Layer Interconnect Structure for Stacked Dies patent-application January 2013

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