Title: Fast process flow, on-wafer interconnection and singulation for MEPV

Abstract

A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.

Inventors:

Okandan, Murat; Nielson, Gregory N.; Cruz-Campa, Jose Luis; Sanchez, Carlos Anthony

Issue Date:

Tue Jan 31 00:00:00 EST 2017

Research Org.:

Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1341870

Patent Number(s):

9559219

Application Number:

14/745,251

Assignee:

Sandia Corporation (Albuquerque, NM)

Patent Classifications (CPCs):

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02E - REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/02118 - {carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
H01L21/2885 - {using an external electrical current, i.e. electro-deposition}
H01L21/311 - Etching the insulating layers {by chemical or physical means
H01L21/76802 - {by forming openings in dielectrics}
H01L21/76871 - {Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers}
H01L21/76877 - {Filling of holes, grooves or trenches, e.g. vias, with conductive material}
H01L23/5386 - {Geometry or layout of the interconnection structure}
H01L31/02008 - {for solar cells or solar cell modules}
H01L31/02021 - {for solar cells
H01L31/022441 - {Electrode arrangements specially adapted for back-contact solar cells}
H01L31/0516 - {specially adapted for interconnection of back-contact solar cells}
H01L31/061 - the potential barriers being of the point-contact type
H01L31/18 - Processes or apparatus peculiar to the manufacture or treatment of these devices or of parts thereof
H01L31/1876 - {Particular processes or apparatus for batch treatment of the devices}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02E - REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

Y02E10/50 - Photovoltaic [PV] energy

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DOE Contract Number:  

AC04-94AL85000

Resource Type:

Patent

Resource Relation:

Patent File Date: 2015 Jun 19

Country of Publication:

United States

Language:

English

Subject:

36 MATERIALS SCIENCE