Via configuration for wafer-to-wafer interconnection

Title: Via configuration for wafer-to-wafer interconnection

Abstract

A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.

Inventors:: Jones, Adam

Issue Date:: 2019-03-05

Research Org.:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1525011

Patent Number(s):: 10224312

Application Number:: 15/603,100

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Classifications (CPCs):: H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L24/16 - {of an individual bump connector}
H01L2224/08121 - the connected bonding areas being not aligned with respect to each other
H01L2224/08147 - the bonding area connecting to a bonding area disposed in a recess of the surface of the body
H01L2224/13006 - Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
H01L24/80 - {Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}
H01L2225/06568 - the devices decreasing in size, e.g. pyramidical stack
H01L2224/05647 - Copper [Cu] as principal constituent
H01L2224/80805 - involving forming a eutectic alloy at the bonding interface
H01L25/50 - {Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
H01L24/13 - {of an individual bump connector}
H01L2224/13082 - Two-layer arrangements
H01L2224/05567 - the external layer being at least partially embedded in the surface
H01L2224/16145 - the bodies being stacked
H01L2225/06527 - Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
H01L2224/05559 - non conformal layer on a patterned surface
H01L24/05 - {of an individual bonding area}
H01L24/09 - {of a plurality of bonding areas}
H01L24/08 - {of an individual bonding area}
H01L25/0657 - {Stacked arrangements of devices}
H01L2225/06513 - Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
H01L24/06 - {of a plurality of bonding areas}
H01L2224/13014 - being circular or elliptic
H01L2924/00014 - the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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DOE Contract Number:: NA0003525

Resource Type:: Patent

Resource Relation:: Patent File Date: 2017-05-23

Country of Publication:: United States

Language:: English

Citation Formats


                    Jones, Adam. Via configuration for wafer-to-wafer interconnection.  United States: N. p., 2019. 
        Web.

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                    Jones, Adam. Via configuration for wafer-to-wafer interconnection.  United States.

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                    Jones, Adam. Tue .  
        "Via configuration for wafer-to-wafer interconnection".  United States.  https://www.osti.gov/servlets/purl/1525011.

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@article{osti_1525011,

  title        = {Via configuration for wafer-to-wafer interconnection},

  author       = {Jones, Adam},

  abstractNote = {A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {3}

}

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Works referenced in this record:

Via configuration with decreased pitch and/or increased routing space
patent, March 2000

Blish, II, Richard C.
US Patent Document 6,037,547
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6037547

Information visualization system
patent, July 2011

Rusu, Adrian; Santiago, III, Confesor
US Patent Document 7,984,389
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7984389

Systems and methods for visualization of data analysis
patent, March 2015

Carlsson, Gunnar; Sexton, Harlan B.; Singh, Gurmeet
US Patent Document 8,972,899
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8972899

Three-dimensional stacked structured ASIC devices and methods of fabrication thereof
patent, November 2015

Shinde, Subhash L.; Teifel, John R.; Flores, Richard S.
US Patent Document 9,190,392
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9190392

Semiconductor wafer bonding incorporating electrical and optical interconnects
patent, April 2016

El-Ghoroury, Hussein S.; Chuang, Chih-Li; Yadavalli, Kameshwar
US Patent Document 9,306,116
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9306116

Bonded stacked wafers and methods of electroplating bonded stacked wafers
patent, May 2016

Zou, Quanbo; Sridhar, Uppili; Kelkar, Amit S.
US Patent Document 9,331,048
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9331048

3D die stacking structure with fine pitches
patent, June 2016

Yu, I., Chen-Hua; Chen, Chen-Shien; Hu, Yen-Chang
US Patent Document 9,379,078
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9379078

Combination of TSV and back side wiring in 3D integration
patent, January 2017

Batra, Pooja R.; Golz, John W.; Iyer, Subramanian S.
US Patent Document 9,536,809
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9536809

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Title: Via configuration for wafer-to-wafer interconnection

Abstract

Citation Formats

Via configuration with decreased pitch and/or increased routing space patent, March 2000

Information visualization system patent, July 2011

Systems and methods for visualization of data analysis patent, March 2015

Three-dimensional stacked structured ASIC devices and methods of fabrication thereof patent, November 2015

Semiconductor wafer bonding incorporating electrical and optical interconnects patent, April 2016

Bonded stacked wafers and methods of electroplating bonded stacked wafers patent, May 2016

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Via configuration with decreased pitch and/or increased routing space
patent, March 2000

Information visualization system
patent, July 2011

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patent, March 2015

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patent, November 2015

Semiconductor wafer bonding incorporating electrical and optical interconnects
patent, April 2016

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patent, May 2016

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patent, June 2016

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patent, January 2017