Via configuration for wafer-to-wafer interconnection
Abstract
A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE National Nuclear Security Administration (NNSA)
- OSTI Identifier:
- 1525011
- Patent Number(s):
- 10224312
- Application Number:
- 15/603,100
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- NA0003525
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2017-05-23
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Jones, Adam. Via configuration for wafer-to-wafer interconnection. United States: N. p., 2019.
Web.
Jones, Adam. Via configuration for wafer-to-wafer interconnection. United States.
Jones, Adam. Tue .
"Via configuration for wafer-to-wafer interconnection". United States. https://www.osti.gov/servlets/purl/1525011.
@article{osti_1525011,
title = {Via configuration for wafer-to-wafer interconnection},
author = {Jones, Adam},
abstractNote = {A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {3}
}
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