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Title: Fast process flow, on-wafer interconnection and singulation for MEPV

A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.
Inventors:
; ; ;
Issue Date:
OSTI Identifier:
1377855
Assignee:
Sandia Corporation SNL-A
Patent Number(s):
9,748,415
Application Number:
15/360,553
Contract Number:
AC04-94AL85000
Resource Relation:
Patent File Date: 2016 Nov 23
Research Org:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE

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A Method for Fabricating Pixelated Silicon Device Cells
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