Bifurcated method and apparatus for floating point addition with decreased latency time

Patent · Thu Jan 01 00:00:00 EST 1987

OSTI ID:866121

Farmwald, Paul M ^[1]

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1. Livermore, CA

Apparatus for decreasing the latency time associated with floating point addition and subtraction in a computer, using a novel bifurcated, pre-normalization/post-normalization approach that distinguishes between differences of floating point exponents.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• DOE Contract Number: W-7405-ENG-48
• Assignee: United States of America as represented by United States (Washington, DC)
• Patent Number(s): US 4639887
• OSTI ID: 866121
• Country of Publication: United States
• Language: English

Related Subjects

bifurcated
method
apparatus
floating
addition
decreased
latency
time
decreasing
associated
subtraction
computer
novel
pre-normalization
post-normalization
approach
distinguishes
differences
exponents
latency time
/708/