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Bifurcated method and apparatus for floating point addition with decreased latency time

Patent ·
OSTI ID:866121
 [1]
  1. Livermore, CA
+ Show Author Affiliations
Apparatus for decreasing the latency time associated with floating point addition and subtraction in a computer, using a novel bifurcated, pre-normalization/post-normalization approach that distinguishes between differences of floating point exponents.
Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA
DOE Contract Number:
W-7405-ENG-48
Assignee:
United States of America as represented by United States (Washington, DC)
Patent Number(s):
US 4639887
OSTI ID:
866121
Country of Publication:
United States
Language:
English

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Related Subjects

/708/
addition
apparatus
approach
associated
bifurcated
computer
decreased
decreasing
differences
distinguishes
exponents
floating
latency
latency time
method
novel
post-normalization
pre-normalization
subtraction
time