Apparatus and method for implementing power saving techniques when processing floating point values
Patent
·
OSTI ID:1397247
An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.
- Research Organization:
- Intel Corporation, Santa Clara, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B600738
- Assignee:
- Intel Corporation
- Patent Number(s):
- 9,779,465
- Application Number:
- 14/581,600
- OSTI ID:
- 1397247
- Resource Relation:
- Patent File Date: 2014 Dec 23
- Country of Publication:
- United States
- Language:
- English
Similar Records
Low energy consumption mantissa multiplication for floating point multiply-add operations
Generating and executing programs for a floating point single instruction multiple data instruction set architecture
Fixed-rate compressed floating-point arrays
Patent
·
Tue Sep 03 00:00:00 EDT 2019
·
OSTI ID:1397247
+1 more
Generating and executing programs for a floating point single instruction multiple data instruction set architecture
Patent
·
Tue Apr 16 00:00:00 EDT 2013
·
OSTI ID:1397247
Fixed-rate compressed floating-point arrays
Software
·
Sun Mar 30 00:00:00 EDT 2014
·
OSTI ID:1397247