Bifurcated method and apparatus for floating point addition with decreased latency time

Patent · Tue Jan 27 04:00:00 EST 1987

OSTI ID:6721431

Farmwald, P M

This patent describes a method for performing floating point addition of a pair of floating point binary numbers each expressed as a mantissa and an exponent. The method comprises the steps of alignment of the mantissas, addition of the aligned mantissas and postnormalization of the mantissa of the sum. The improvement described here comprises: comparing the exponents of the two floating point numbers prior to the alignment step; simultaneously performing two separate calculations along first and second separate parallel paths as follows: calculating a first sum in the first path as if the difference of the exponents is either 0 or 1, including performing the alignment step by at most a one place right shift of one mantissa; simultaneously calculating a second sum in the second path as if the difference of the exponents is greater than 1, including performing the postnormalization step by at most a one place shift of the mantissa of the second sum; selecting between the first sum and the second sum after simultaneously performing the two calculations.

• Assignee: Dept. of Energy, Washington, DC
• Patent Number(s): US 4639887
• OSTI ID: 6721431
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ANALYTICAL SOLUTION
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
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EQUATIONS
MATHEMATICS
PARALLEL PROCESSING
PROGRAMMING
TIME DEPENDENCE