Test generation by fault sampling: A new approach for VLSI circuits
The problem of test generation for VLSI circuits and the concepts of testability analysis were studied. The test-generation problem for combinational circuits is known to NP-complete in the circuit size. Heuristics to solve this problem exist. The solution has two major costs associated with the test-generation and fault-simulation steps. For large sequential circuits, the fault-simulation costs are dominant. A new technique that reduces the fault simulation costs is introduced here. Testability of a circuit used to guide the design and test process of a circuit is discussed. A new method of evaluating the testability of a circuit while performing test generation is introduced. It has several advantages over other proposed methods: (a) the evaluation effort is only incremental over standard test generation; (b) results are applicable to random as well as deterministic test vectors; (c) results are computed on the fly and refined continuously, hence they can be used to provide useful feedback to the test-generation process itself; and (d) the evaluation is independent of the circuit structure and, hence, applicable equally to sequential as well as combinational circuits. Experimental results about test generation and testability evaluation for benchmark circuits of up to several thousand logical gates are presented.
- Research Organization:
- Nebraska Univ., Lincoln, NE (USA)
- OSTI ID:
- 7248554
- Country of Publication:
- United States
- Language:
- English
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