Logic verification and test generation for VLSI circuits

Thesis/Dissertation · Tue Dec 31 23:00:00 EST 1985

OSTI ID:6973275

Wei, R

This dissertation focuses on efficient test-pattern generation, efficient redundancy identification, and efficient logic verification for scan-testable VLSI circuits. For logic verification, applicable circuits also include non-scan-testable VLSI circuits for which correspondence of memory elements between two-verified circuits can be established. New approaches to solving these problems and the systems implementing these approaches are presented. For efficient test-pattern generation of multi-level combinational circuits, a new front-end heuristic test pattern generator, VICTOR-III, a new line-justification algorithm for the D-algorithm and its derivatives, DIJUST, and a method for test-set compaction, BUSIM, are presented. MAHJONG, a user-configurable automatic test-pattern generation system employing these techniques was developed. For efficient redundancy identification, a system of three programs: VICTOR-III, TRIP, and TAUT, to be executed in that order, is presented. The set of faults is gradually classified into the set of irredundant faults and truly redundant faults through the introduction of potentially redundant faults. For efficient logic verification, PROTEUS, a system of many logic verification programs, mostly based on newly developed algorithms, is presented. Direct comparison of these programs is performed and many important conclusions are drawn.

• Research Organization: California Univ., Berkeley (USA)
• OSTI ID: 6973275
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210 -- Supercomputers-- (1987-1989)
ALGORITHMS
COMPARATIVE EVALUATIONS
COMPUTER CODES
ELECTRONIC CIRCUITS
FAULT TREE ANALYSIS
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
SYSTEM FAILURE ANALYSIS
SYSTEMS ANALYSIS