Self-testing VLSI circuits
A self-testing circuit design methodology is developed for off-line testing of regular or nearly regular VLSI (very large scale integrated) circuits. It is based on four major design concepts: circuit partitioning, regularization to produce identical subcircuits (partitions), parallel testing of partitions, and fault detection by direct comparison of response streams from the partitions. Existing concepts of regular circuits (iterative logic arrays) are generalized to include array-like circuits that contain several cell types and are moderately irregular. A heuristic circuit partitioning and regularization method based on subcircuit isomorphism is introduced. An on-chip test generation technique employing nonlinear feedback shift registers is developed to generate test pattern sequences with very high fault coverage. A new way of designing the feedback shift registers is presented which greatly reduces the complexity of the feedback circuits and the number of redundant test patterns. An efficient MOS equality checker is defined that can compare a large number of parallel response streams. The proposed design methodology is applied to the problem of making very large dynamic random access memory (RAM) chips self-testing. Such RAMS are the most widely used VLSI circuits. The physical failure modes, including the difficult neighborhood interference faults, of a typical dynamic RAM are analyzed to identify their testing needs.
- Research Organization:
- Michigan Univ., Ann Arbor (USA)
- OSTI ID:
- 5099930
- Country of Publication:
- United States
- Language:
- English
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