Testing and fault-tolerance aspects of high-density VLSI memory
Presented in this thesis is a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for RAMs and CAMs are developed for a broad class of parametric and pattern-sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. In embedded applications, where neither the address and read/write lines are externally controllable nor are the output lines directly observable, the proposed algorithms were adapted for Built-In Self-Test (BIST) implementation. It is also shown that the proposed design for testability is amenable for random testing in the event BIST hardware cannot be integrated at the site of the memory. Also the on-line fault detection and correction due to alpha-particle-induced soft error and other transients, were investigated. Finally, it was demonstrated how to integrate the concepts of testability and fault tolerance within a chip so that during normal operation the testable logic can be reconfigured into an error-correcting circuit.
- Research Organization:
- Illinois Univ., Urbana, IL (USA)
- OSTI ID:
- 5214229
- Country of Publication:
- United States
- Language:
- English
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