Design of defect/fault-tolerant, testable VLSI systems
This dissertation addresses three areas. It proposes a simple methodology to quantify the metrics of area, performance, testability, and yield of a VLSI system. Change in these metrics when the design is modified to make it more testable or defect/fault-tolerant represent the cost/performance of that technique. The Tree Random Access Memory Architecture, is then presented. This is a methodology for the design of future multi-megabit Dynamic Random Access Memories so that they are easily testable, have good performance, low refresh time, and are defect/fault-tolerant. The increase in area is compensated by enhanced yield. Finally, several related issues are discussed: extensions of the TRAM architecture, wafer-scale memory systems, testing encoded memories, evaluating the cost/performance of using partial scan as a design for testability, developing benchmark models for other architectures, and integrating the modeling techniques presented.
- Research Organization:
- Massachusetts Univ., Amherst, MA (USA)
- OSTI ID:
- 6045933
- Country of Publication:
- United States
- Language:
- English
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