Testable structures for CMOS VLSI circuits

Thesis/Dissertation · Thu Jan 01 04:00:00 EST 1987

OSTI ID:7245068

Liu, D L

This thesis presents three classes of circuit structures that can be used to design easily testable CMOS VLSI circuits. These testable structures are a built-in self-test (BIST) PLA, a fully-testable static CMOS combinational circuit, and two self-test structures for application-specific ICs (ASICs). Testing CMOS VLSI circuits is a challenging task. Conventional automatic test-pattern generation (ATPG) programs are not adequate to generate test patterns because of the complexity of VLSI circuits. Many BIST schemes are not suitable for designing large embedded PLAs because they cannot perform self-test at normal operating speed, and take too much area. The BIST PLA described solves these problems by using a sequential parity-checking technique to achieve high testing speed and novel circuit structures to minimize hardware overhead. CMOS switch-level (stuck-open and stuck-on) faults are hard to detect because stray circuit delays can invalidate stuck-open fault patterns and many stuck-on faults are not detectable. This thesis presents a fully-testable structure for combinational circuits. Pseudorandom testing techniques were used to self-test ASICs. However, these techniques require lengthy fault simulation, only consider single stuck-at faults, and may not provide high fault coverage due to the existence of random-pattern-resistant faults.

• Research Organization: Stanford Univ., CA (USA)
• OSTI ID: 7245068
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
FAULT TOLERANT COMPUTERS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
SEMICONDUCTOR DEVICES
SWITCHING CIRCUITS
TESTING
TRANSISTORS