Digital circuits: random testing and timing

Thesis/Dissertation · Thu Jan 01 04:00:00 EST 1987

OSTI ID:7245044

Wagner, K D

This thesis establishes a mathematical foundation for stuck-at-fault testing and delay testing of integrated circuits using randomly generated test vectors. In addition, it studies the close relationship between system timing and circuit-switching behavior in high-speed computers; understanding this relationship leads to the development of new design and test methodologies. Pseudorandom testing is a common technique for both built-in self-test (BIST) applications and more-conventional testing with an external tester. It requires no test-pattern generation, only fault-free circuit simulation. Analysis of pseudorandom testing with respect to single stuck-at faults produces expressions for test length and measures of test quality, including expected fault coverage. It is shown that the random-test model often used as an approximation for pseudorandom testing can be discarded in favor of the pseudorandom test model, which is more accurate, easier to use, and predicts shorter test lengths. The work examines the use of random and pseudorandom test vector pair generation as an alternative to algorithmic test pattern generation for delay testing,Calculation of the test length required to detect a delay fault with a specified test confidence is presented. New weakened conditions are defined for the selection of test vector pairs capable of detecting delay faults.

• Research Organization: Stanford Univ., CA (USA)
• OSTI ID: 7245044
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
FAULT TREE ANALYSIS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
SUPERCOMPUTERS
SWITCHING CIRCUITS
SYSTEM FAILURE ANALYSIS
SYSTEMS ANALYSIS
TENSORS
TESTING
TIMING CIRCUITS
VECTORS