Built-in self-test resources for fault-tolerant VLSI environments
Chip-level built-in self-test (BIST) techniques were developed to enhance testability at the manufacturing stage and have also been extended to the system level. In this extended capacity, BIST features can be used to increase the reliability and dependability of the functional system. This dissertation investigates the modeling and analysis of built-in self-test resources in a fault-tolerant VLSI environment. The BIST circuitry is utilized as a fault-detection mechanism for gracefully degrading systems employing dynamic redundancy. Specific models are evaluated under the constraints of fixed test time and fixed resource assumptions. For a fixed-test time model, the additional overhead of distributed BIST techniques, as compared to centralized schemes, is justified when area-utilization measures are considered. These measures assess system maintenance and test cost beyond the initial BIST hardware overhead penalty. The specific BIST technique employed (centralized or distribute) is also shown to have a significant influence upon instantaneous and cumulative reward measures. It is shown that optimal system performability can be achieved by dedicating an appropriate fraction of the VLSI real estate to maintenance resources.
- Research Organization:
- Pennsylvania State Univ., University Park, PA (USA)
- OSTI ID:
- 7129061
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
990200* -- Mathematics & Computers
COMPUTERS
DATA PROCESSING
DIGITAL COMPUTERS
DISTRIBUTED DATA PROCESSING
ELECTRONIC CIRCUITS
FAULT TOLERANT COMPUTERS
FAULT TREE ANALYSIS
FUNCTIONAL MODELS
INTEGRATED CIRCUITS
MAINTENANCE
MICROELECTRONIC CIRCUITS
PERFORMANCE
PROCESSING
SYSTEM FAILURE ANALYSIS
SYSTEMS ANALYSIS
TESTING