Test scheduling and control for VLSI built-in self-test
In this paper, the problem of exploiting parallelism in the testing of VLSI circuits with built-in self-test (BIST) is examined in detail using a broader modeling foundation and new algorithms. A hierarchical model for VLSI circuit testing is introduced. A test resource sharing model is employed to exploit the potential parallelism. Based on this model, very efficient suboptimum algorithms are proposed during defining test schedules for both the equal length test and unequal length test cases. For the unequal length test case, three different scheduling disciplines are defined and scheduling algorithms are given for two of the three cases. Data on algorithm performance are presented. The issue of the control of the test schedule is also addressed, and a number of structures are proposed for implementation of control.
- Research Organization:
- Dept. of Electrical and Computer Engineering, Syracuse Univ., Syracuse, NY (US)
- OSTI ID:
- 6450006
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 37:9; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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