Test-time reduction for high-performance VLSI system implementations
Testing high-performance VLSI systems containing pipelines and multifunctional units is a formidable task due to their complexity and limited accessibility. A problem of particular importance is the excessively long testing time required by serial execution of tests on the various major blocks in the system. Exploitation of the available testing parallelism to achieve test time reduction, primarily by test scheduling, is important in both production and field-maintenance environments. Thus, the problem addressed here is utilizing the available testing parallelism in a machine and introducing further test parallelism by the addition of testability features to achieve the shortest possible testing time for a set of design tradeoffs. A broader modeling foundation that encompasses both dimensions, space and time, of test parallelism is outlined. A simple scheduling model and techniques are developed for efficient scheduling algorithm design. An optimal solution and effective heuristic algorithms for scheduling tests are presented. Good performance was demonstrated by experimental implementations of the heuristic algorithms.
- Research Organization:
- Wisconsin Univ., Madison, WI (USA)
- OSTI ID:
- 6046022
- Country of Publication:
- United States
- Language:
- English
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