Fast and area-efficient VLSI adders
Area-time tradeoffs have been an important topic in VLSI research. This is because the cost of fabricating a circuit is an exponential function of its area. As a result, optimizing the area of a VLSI design is much more important than optimizing the speed of an algorithm. This dissertation examines area-time tradeoffs in VLSI for prefix computation using graph representations of the problem. Since the problem is intimately related to binary addition, results obtained lead to design of area-time efficient VLSI adders. This is a major goal of the work: to design very low latency-addition circuitry that is also area-efficient. To this end, a new graph representation is presented for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the author designed VLSI adders having area A = O(n log n) whose delay time is the lowest possible value, i.e., the fastest possible area-efficient VLSI adder. For the large number of inputs, the pipelined model of prefix circuit is presented. Also presented is a fault-tolerant model for the developed prefix circuit, based on the partitioning of the network.
- Research Organization:
- Massachusetts Univ., Amherst (USA)
- OSTI ID:
- 6355081
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPUTER GRAPHICS
COMPUTERS
DESIGN
DIGITAL COMPUTERS
EFFICIENCY
ELECTRONIC CIRCUITS
FAULT TOLERANT COMPUTERS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PROGRAMMING
SURFACE AREA
SURFACE PROPERTIES