Knowledge based system for designing testable VLSI circuits
A knowledge based system that can be used for designing testable VLSI circuits is described. First, a model for capturing circuit designs which incorporates all the relevant aspects of a design from the testing point of view is introduced. Next, a methodology that incorporates structural, behavioral, qualitative, and quantitative aspects of known design for testability (DFT) techniques is presented. A frame model for representing testable design methodologies is then introduced. This methodology framework provides a designer with a systematic design for testability synthesis approach. The process of partitioning a design into subcircuits which can be processed individually is examined next. A three-phase partitioning scheme is presented. The new concept of an I-path, which is used to transfer data from one place in the circuit to another, is introduced. This powerful concept represents an important departure from previous efforts in the DFT field. The mechanism and rules that govern the process of applying testable design methodologies to circuit partitions are presented. Measures for evaluating and comparing different testable designs are also developed. The concept of a test plan which describes how a test methodology is to execute in a actual circuit is introduced.
- Research Organization:
- University of Southern California, Los Angeles (USA)
- OSTI ID:
- 5254958
- Country of Publication:
- United States
- Language:
- English
Similar Records
Testable structures for CMOS VLSI circuits
Test generation by fault sampling: A new approach for VLSI circuits