Test generation and fault detection for VLSI PPL circuits
The problem of design for testability of PPL logic circuits is addressed. A test-generation package was developed which utilizes the special features of PPL logic to generate high fault coverage test vectors at a reduced computational cost. The test strategy assumes that one of the scan design techniques is used. A new methodology for test-vectors compaction without compromising the fault coverage is also proposed. A fault-oriented test-generation algorithm combined with a heuristic test-generation algorithm are the essential ingredients of this package. The fault-oriented algorithm uses a modified D-algorithm which includes look-ahead features and a new seven-valued logic to improve the average speed of the test-generation process. Fault coverages in the 90% range were obtained using the test sequences generated by this package.
- Research Organization:
- Utah Univ., Salt Lake City (USA)
- OSTI ID:
- 7055374
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
COMPUTERS
DESIGN
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
FAULT TOLERANT COMPUTERS
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
TESTING