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Parallel algorithms and VLSI architectures for robotics and assembly scheduling

Thesis/Dissertation ·
OSTI ID:7184509
This research addresses two intensive computational problems of designing VLSI architectures for robotic computations and of implementing the assembly scheduling problem on a highly parallel artificial neural network. In designing VLSI architectures for a complex computational robotic task, the functional decomposition of the task into a set of computational modules can be represented as an acyclic data flow graph (ADFG) which can be mapped into the VLSI architecture by an existing systolization procedure. An efficient graph-decomposition technique was developed that utilizes the critical path concept to decompose a large-scale directed ADFG into a set of connected subgraphs, and the integer linear optimization technique can be used to solve the buffer assignment problem in each subgraph in pseudo-polynomial time. The other equally important computational problem is the NP-complete assembly scheduling problem which is difficult to be solved by traditional machines. The real-time assembly scheduling problem is characterized by a bipartite graph model and re-formulated as a two-stage optimization.
Research Organization:
Purdue Univ., Lafayette, IN (USA)
OSTI ID:
7184509
Country of Publication:
United States
Language:
English

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