Mapping algorithms to VLSI array processors
A VLSI array processor, such as the systolic or wavefront array, consists of a number of modular processing elements (PEs) connected in a regular array structure and solves a specific algorithm efficiently. This dissertation addresses the issues of mapping algorithms to VLSI array processors. The first step in the mapping is to express the algorithms in a suitable form, known as the dependence graph (DG), which explicitly displays the data dependencies in the algorithm. The next step is to map the DG to a signal-flow graph (SFG), which is a synchronous computing network frequently used in the signal-processing literature. This SFG can then be transformed to a synchronous systolic array or to an asynchronous wavefront array. All three stages of the mapping process can be formally defined. The mapping from the DG to the SFG is by a linear projection and a linear scheduling which simplify the control of the array. A cut-set procedure is used to convert the SFG to a synchronous systolic array, while a wavefront array can be derived from the SFG by a DFG (Dataflow Graph) analysis method. Much effort is devoted to the optimal array designs. Projection direction and scheduling can be determined to yield an optimal SFG design.
- Research Organization:
- University of Southern California, Los Angeles (USA)
- OSTI ID:
- 6889991
- Country of Publication:
- United States
- Language:
- English
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