On supercomputing with systolic/wavefront array processors
Tremendous progress has been made on several promising parallel architectures for scientific computations, including a variety of digital filters, fast Fourier transform (FFT) processors, data-flow processors, systolic arrays, and wavefront arrays. This paper describes these computing networks in terms of signal-flow graphs (SFG) or data-flow graphs (DFG), and proposes a methodology of converting SFG computing networks into synchronous systolic arrays or data-driven wavefront arrays. Both one- and two-dimensional arrays are discussed theoretically, as well as with illustrative examples. A wavefront-oriented programming language, which describes the (parallel) data flow in systolic/wavefront-type arrays, is presented. The structural property of parallel recursive algorithms points to the feasibility of a Hierarchical Iterative Flow-Graph Design (HIFD) of VLSI Array Processors. The proposed array processor architectures, will have significant impact on the development of future supercomputers.
- Research Organization:
- Department of Electrical Engineering, University of Southern California, Los Angeles, CA
- OSTI ID:
- 5083359
- Journal Information:
- Proc. IEEE; (United States), Journal Name: Proc. IEEE; (United States) Vol. 72:7; ISSN IEEPA
- Country of Publication:
- United States
- Language:
- English
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