Analysis of systolic and systolic-type arrays

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:5127821

Jover, J M

Synchronous, multiprocessor systems interconnected by fixed links are studied. These special-purpose systems, called systolic-type arrays, perform specific algorithms at a higher throughput rate than the sequential architecture of van Neumann. The main contributions of this thesis are the analysis of systolic-type arrays, and the design of one such complex system. In the analysis problem the topology of the network, the function performed by each processor (including timing information), and the input data streams are given. I/O algorithm performed by the array, and the iteration interval (i.e., the time between two consecutive input samples) are to be determined. Solution to the analysis problem turns out to be based on the simple, at least in retrospect, observation that analysis is the reverse of synthesis (design). In design, the start is with a mathematical algorithm and a representation of it as a signal flow graph (SFG) in which the computations (function evaluations) are presented by delay-free (instantaneous) blocks and the index shifts in the sequences processed by the algorithm are all lumped into so-called z/sup -1/ blocks. In the analysis problem, start is also with a physical implementation described by its computational blocks, their associated processing times, and their interconnections. Also presented is parallel architecture for the measurement update step of the Kalman filter, which estimates a vector parameter.

• Research Organization: Stanford Univ., CA (USA)
• OSTI ID: 5127821
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
DESIGN
MATHEMATICAL LOGIC
NETWORK ANALYSIS
PARALLEL PROCESSING
PROGRAMMING