Bit-level systolic arrays
In this dissertation the author considered the design of bit - level systolic arrays where the basic computational unit consists of a simple one - bit logic unit, so that the systolic process is carried out at the level of individual bits. In order to pursue the foregoing research, several areas have been studied. First, the concept of systolic processing has been investigated. Several important algorithms were investigated and put into systolic form using graph-theoretic methods. The bit-level, word-level and block-level systolic arrays which have been designed for these algorithms exhibit linear speedup with respect to the number of processors and exhibit efficiency close to 100%, even with low interprocessor communication bandwidth. Block-level systolic arrays deal with blocks of data with block-level operations and communications. Block-level systolic arrays improve cell efficiency and are more efficient than their word-level counterparts. A comparison of bit-level, word-level and block-level systolic arrays was performed. In order to verify the foregoing theory and analysis a systolic processor called the SPRINT was developed to provide and environment where bit-level, word-level and block-level systolic algorithms could be confirmed by direct implementation rather than by computer simulation. The SPRINT is a supercomputer class, 64-element multiprocessor with a reconfigurable interconnection network. The theory has been confirmed by the execution on the SPRINT of the bit-level, word-level, and block-level systolic algorithms presented in the dissertation.
- Research Organization:
- California Univ., Davis, CA (USA)
- OSTI ID:
- 6093734
- Country of Publication:
- United States
- Language:
- English
Similar Records
A systolic array for efficient matrix-matrix multiplication. [SPRINT]
A systolic array for efficient execution of the radon and inverse radon transforms