Algorithm implementation and design of reconfigurable mixed systolic arrays
This thesis presents a methodology for algorithm implementation and design of a class of reconfigurable multiprocessor architectures called the mixed systolic array (MSA). In the MSA architecture, switching cells are mixed with computation cells to achieve flexibility in the data-flow patterns. This architecture broadens the scope of systolic arrays by achieving reconfigurability, algorithmic flexibility, and fault tolerance. The level sensitive scan design (LSSD) technique is employed to load and implement the distributed control structure required to establish a desired interconnection pattern on the MSA. The control structure for a particular configuration is loaded into the array as a binary vector in a bit serial fashion. This approach enhances testability and incorporates fault tolerance in the MSA structures. Efficient implementation of algorithms on VLSI structures requires exploitation of parallelism in the algorithm and mapping of the algorithm communication structure in the processor interconnection structure. This thesis presents a general mathematical model for formally representing reconfigurable MSA architectures and a step-by-step procedure for implementing a given algorithm into the MSA structure by generating the control code required to reconfigure the array.
- Research Organization:
- Michigan State Univ., East Lansing (USA)
- OSTI ID:
- 5641021
- Country of Publication:
- United States
- Language:
- English
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