Impact and limitations of interconnect technology on VLSI and restructurable VLSI design

Conference · Fri Dec 31 23:00:00 EST 1982

OSTI ID:5210006

Mangir, T E

Interconnect technologies for VLSI are reviewed, and interconnect techniques for restructurable and programmable VLSI are presented. Interconnect RC time delays do not scale down with scaled technology and become the limiting factor for the speed of VLSI computations. Proposed signal processing architectures (such as systolic arrays, wavefront processors, array processors) suggest that operands will arrive from different processing elements, to be operated on at a specific processing site. This implies that the delays introduced by the interconnections between stages will set the physical limits to communication between processors, and to the overall performance of VLSI. 26 references.

• OSTI ID: 5210006
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARCHITECTURE
ARRAY PROCESSORS
COMMUNICATIONS
ELECTRONIC CIRCUITS
IMAGE PROCESSING
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PERFORMANCE
PROCESSING
PROGRAMMING
TIME DELAY