A decomposition approach for balancing large-scale acyclic data flow graphs

Journal Article · Mon Jan 01 04:00:00 EST 1990 · IEEE (Institute of Electrical and Electronics Engineers) Transactions on Computers; (USA)

DOI:https://doi.org/10.1109/12.46279· OSTI ID:7222615

Chang, P R ^[1]; Lee, C S.G. ^[2]

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1. Advanced Technology Center of ERSO of Industrial Technology Research Institute, Chu-Tung, Taiwan, Republic of China (TW)
2. Purdue Univ., Lafayette, IN (USA). School of Electrical Engineering

In designing VLSI architectures for a complex computational task, the functional decomposition of the task into a set of computational modules can be represented as a directed task graph, and the inclusion onf input dta modifies the task graph to an acylic data flow graph (ADFG). Due to different paths of traveling and computation time of each computational module, operands may arrive at multiinput modules at different arrival times, causing a longer pipelined time. Delay buffers may be inserted along various paths to balance the ADFG to achieve maximum pipelining. This paper presents an efficient decomposition technique which provides a more systematic approach in solving the optimal buffer assignment problem of an ADFG with a large number of computational nodes. The buffer assignment problem is formulated as an integer linear optimization problem which can be solved in pseudopolynomial time. Examples are given to illustrate the proposed decomposition technique.

• OSTI ID: 7222615
• Journal Information: IEEE (Institute of Electrical and Electronics Engineers) Transactions on Computers; (USA), Journal Name: IEEE (Institute of Electrical and Electronics Engineers) Transactions on Computers; (USA) Vol. 39:1; ISSN 0018-9340; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMPUTER CALCULATIONS
DATA-FLOW PROCESSING
DESIGN
ELECTRONIC CIRCUITS
GRAPHS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
OPTIMIZATION
PROGRAMMING