Hierarchical multiprocessor architecture design in VLSI for real-time robotic control applications

Thesis/Dissertation · Wed Jan 01 00:00:00 EST 1986

OSTI ID:5332046

Ling, Y L.C.

This dissertation presents a layered restructurable multiprocessor architecture based on state-of-the-art VLSI technology for the realtime control of robotic applications. This architecture uses two VLSI chips as building blocks - Robotic Scalar Processor (RSP) and Robotic Vector Processor (RVP). These two VLSI processors may be used repeatedly to construct various computing structures to satisfy the computation and communication requirements of various robotic control applications. VLSI design and layout of the RVP have been largely completed. Two test VLSI chips, a 32-bit floating point adder and multiplier, have been set out for fabrication at 3.0 ..mu..m CMOS technology. The floating point adder test chip ha been received and tested. Preliminary testing results have shown that the floating point adder functions properly at 80 ns cycle time. The proposed architecture has been used to implement the Inverse Plant Plus Jacobian Control Algorithm for the control of a six-link robot manipulator. Significant computational performance has been achieved. The resulting VLSI architecture is capable of handling robotic control in real-time environments.

• Research Organization: Ohio State Univ., Columbus (USA)
• OSTI ID: 5332046
• Resource Relation: Other Information: Thesis (Ph. D.)
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTERIZED CONTROL SYSTEMS
REAL TIME SYSTEMS
MANIPULATORS
ROBOTS
INTEGRATED CIRCUITS
CONTROL SYSTEMS
ELECTRONIC CIRCUITS
EQUIPMENT
LABORATORY EQUIPMENT
MATERIALS HANDLING EQUIPMENT
MICROELECTRONIC CIRCUITS
REMOTE HANDLING EQUIPMENT
990210* - Supercomputers- (1987-1989)