Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems

Journal Article · Thu May 01 00:00:00 EDT 1986 · Proc. IEEE; (United States)

DOI:https://doi.org/10.1109/PROC.1986.13532· OSTI ID:5653096

Koren, I; Pradhan, D K

New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emerging area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance and yield improvement techniques. Fault tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. The underlying concepts of fault tolerance at work in these multiprocessor systems are described. These precepts are useful to then present certain techniques that will incorporate fault tolerance integrally into the design. In the second part of the paper, models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques are discussed.

• Research Organization: Depts. of Electrical Engineering and Computer Science, Technion - Israel Inst. of Technology, Haifa 32000
• OSTI ID: 5653096
• Journal Information: Proc. IEEE; (United States), Journal Name: Proc. IEEE; (United States) Vol. 74:5; ISSN IEEPA
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARCHITECTURE
ARRAY PROCESSORS
CIRCUIT THEORY
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
FAULT TOLERANT COMPUTERS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PERFORMANCE
RELIABILITY
RESEARCH PROGRAMS