Diagnosis and reconfiguration of VLSI/WSI array processors
Some fault-tolerant techniques and analytical methods are presented for linear, mesh, and tree array processors which are implemented in Very Large Scale Integration (VLSI) circuits or Wafer Scale Integration (WSI) circuits. Several techniques are developed for testing, diagnosis, on-line fault detection and reconfiguration of array processors. A testing strategy, built-in self-test, is presented for array processors to achieve the C-testability by which the test length is independent of the size of the array. The signature comparison approach is used for diagnostic algorithms. Reconfiguration schemes with two-level redundancy for mesh and tree arrays are described. An on-line fault detection scheme by using redundant cells and blocks are developed. Analytical tools for reliability are given for evaluating the proposed schemes. A yield estimation model for WSI mesh array processors with two-level redundancy is presented. Distributed as well as clustered defects are considered in this model.
- Research Organization:
- State Univ. of New York, Binghamton, NY (USA)
- OSTI ID:
- 5146005
- Country of Publication:
- United States
- Language:
- English
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