Testing and reconfiguration techniques for VLSI processor arrays
Processor arrays considered here are two-dimensional iterative arrays, systolic arrays, and SIMD arrays. Testing for iterative arrays, made of combinational cells, and for systolic arrays is performed with a number of test vectors which is independent of the array size (C-Testability). The main contribution of this work is the extension of the C-testability concept to different directions. Better results than previously published have been accomplished for two-dimensional orthogonal arrays. C-testability has been extended to the more complex case of hexagonal arrays. The C-testability approach has then been applied to the general case of tree structures. This constitutes a contribution to the C-testability theory because of the undecidability property of these structures. The problem of testing multi-dimensional arrays constituted by cells that can be considered as complete microprocessors, was also studied. The main contribution is the definition of a general testing methodology for multi-dimensional array processors such as SIMD arrays, in which cells can execute an instruction set. Fault tolerance of processor arrays was studied, and two algorithms for host-driven dynamic reconfiguration are proposed.
- Research Organization:
- Colorado Univ., Boulder, CO (USA)
- OSTI ID:
- 7020362
- Country of Publication:
- United States
- Language:
- English
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