Reconfigurable processor-array

Book · Sun Jan 01 04:00:00 EST 1989

OSTI ID:5501499

Rushton, A ^[1]

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1. Univ. of Southampton (US)

This book investigates enhancements to the conventional bit-serial PE and offers ways to improve performance when the small-gain parallelism of a single instruction-stream, multiple data-stream (SIMD) class parallel computer architecture is inefficient. The book outlines the development of SIMD-class parallel computer based on processor-arrays. Surprisingly, for many problems, a large array of bit-serial processing elements is a better source of processing power than a small array of complex processors, and the reconfigurable processor-array described here is enhanced with floating-point, multiplication, and data cache facilities to improve the operation of such arrays. The RPA also has features that allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism. The author describes the implementation of the architecture as a chip design, and adds an appendix containing high-level formal description of the processing element in a register-transfer language.

• OSTI ID: 5501499
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ABSTRACTS
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTERS
DESIGN
DIGITAL COMPUTERS
DOCUMENT TYPES
EFFICIENCY
LEADING ABSTRACT
PARALLEL PROCESSING
PROGRAMMING
SUPERCOMPUTERS