Reconfigurable processor-array
Book
·
OSTI ID:6597471
- Univ. of Southampton (GB)
This book investigates enhancements to the conventional bit-serial PE and offers ways to improve performance when the small-grain parallelism of a single instruction-stream, multiple data-stream (SIMD) class parallel computer architecture is inefficient. The author describes the implementation of the architecture as a chip design, and adds an appendix containing high-level formal description of the processing element in a register-transfer language.
- OSTI ID:
- 6597471
- Country of Publication:
- United States
- Language:
- English
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