Nonplanar VLSI arrays with high fault-tolerance capabilities
- Louisiana State Univ., Baton Rouge, LA (USA)
This paper proposes and analyzes some new VLSI architectures for improved fault tolerance. The architecture include structures with two planar layers of processing elements as well as extended cubic designs. The analyses for arrays with various redundancy levels show remarkable improvement in both array yield and processor use over those exhibited by conventional 2-D structures. The improvement can be attributed to the benefits of the third dimension to increase the flexibility in spares allocation. The architectures can readily substitute arrays based on mesh or four nearest-neighbor interconnections. From the fault-tolerance viewpoint the cubic structures offer no appreciable performance improvement over the simpler 2-layer structures.
- OSTI ID:
- 5213239
- Journal Information:
- IEEE (Institute of Electrical and Electronics Engineers) Transactions on Reliability; (USA), Journal Name: IEEE (Institute of Electrical and Electronics Engineers) Transactions on Reliability; (USA) Vol. 38:1; ISSN IEERA; ISSN 0018-9529
- Country of Publication:
- United States
- Language:
- English
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COMPUTER ARCHITECTURE
COMPUTERS
DESIGN
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
FAULT TOLERANT COMPUTERS
HYPERCUBE COMPUTERS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PERFORMANCE
TWO-DIMENSIONAL CALCULATIONS